Method for transmitting data over a data bus with minimized digital inter-symbol interference

ABSTRACT

A method for transmitting data via a data bus with minimized digital control and data inter-symbol interference. The voltage level on the bus is not permitted to reach the bus negated quiescent voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitry to detect a first segment of data transferred over the bus. A pause time is enabled after the bus has been at idle/paused for a prolonged period. After the first segment of data has been transferred, the method returns to normal operation by pausing for a normal period of time for data detection circuitry to detect subsequent segments of data transferred over the bus. Additionally, during prolonged synchronous data transfers with unchanged data bits, the data bus is inverted and driven for further regulating the data bus voltage.

FIELD OF THE INVENTION

[0001] The invention relates generally to transmitting binary data overa data transmission line and more precisely to transmitting binary dataover a data transmission line with minimized digital inter-symbolinterference.

BACKGROUND OF THE INVENTION

[0002] As illustrated in FIG. 1, data is typically transmitted back andforth between a host computer system 10 and peripheral devices, such asdisk drives 5, tape drives 6, or printers 7, over a data communicationbus 15. The data communication bus 15 couples the host computer system10 and the peripheral devices 5, 6, and 7 together and enables theexchange of data between the system and the devices. One type of datacommunication bus is a Small Computer System Interconnect (SCSI) databus. A SCSI data bus can be configured in different ways and has severalmodes of operation. One configuration and mode of operation is known asSCSI wide bus which includes a sixteen bit data bus with associatedcontrol signals such as Busy (BSY), Select (SEL), Control/Data (C/D),Input/Output (I/O), Message (MSG), Request (REQ), Acknowledge (ACK),Attention (ATN), and Reset (RST). The SCSI data bus is connected to thehost computer system 10 via a host adapter 12 and is connected toperipheral devices 5, 6, and 7 via device controllers 8, 9, and 11. Thedevice controller is matched to the specific type of device connected tothe SCSI bus as shown in FIG. 1. The SCSI data bus 15 may be configuredto include a plurality of peripheral devices daisy chained together,where both the host computer, and the last device connected to the bus(furthest from the host) are terminated with a bus terminator 16. Thebus terminator 16 includes circuitry for regulating the maximum and theminimum voltage levels on the SCSI data bus 15.

[0003] Referring to FIGS. 2A and 2B, the maximum and minimum voltagethresholds for data detection (V-one and V-zero) is sensed by a datadetection circuit 13. Each threshold is a fixed d.c. voltage levelconnected to a signal line of the bus 15, which is driven by a driver14. This fixed d.c. threshold level is typically defined between theterminator voltage boundaries (+V-term and −V-term). Both the hostadapter and the device controllers contain driver circuitry 14 fordriving, and receive circuitry 13 for receiving, the data and logiccircuits (not shown in FIG. 2A) for directing data flow and processingoperations.

[0004] When information is transferred between the host computer systemand any one of the plurality of peripheral devices, a handshakingprotocol is used to initiate data requests and acknowledge that suchrequests have been completed. A REQ control signal may be asserted by aninitiating device to request that the target either write or read datato/from the initiating device. An ACK control signal may be asserted bythe target device to acknowledge that the target device successfullysent or received data.

[0005] A problem can occur when the SCSI data bus idles with no datatransfers for a prolonged period of time. In this instance the voltagelevel on the bus will rise to the maximum voltage value defined by thebus terminators, called herein the quiescent negated voltage level. Whena REQ is asserted, the REQ control circuitry provides a predeterminedfixed window of time for the REQ to be sensed by data detectioncircuitry before subsequent REQs are asserted. Since the bus voltage isat the negated quiescent voltage level during prolonged idles, the REQmust make a larger signal level swing than during synchronous operationin order to reach a level capable of being sensed as a REQ by thedetection circuitry. In one failure mode, there is insufficient time forthe REQ signal to be sensed by the data detection circuitry during afirst assertion of REQ before a subsequent REQ is asserted.Consequently, REQ data transmitted on other lines of the bus during thefirst REQ pulse may not be sensed correctly by the detection circuitryand may be lost. A second failure mode occurs when the REQ signal is notsensed at all by the REQ detection circuitry within predetermined timeconstraints. These failure modes are hereby defined as digital controlsignal Inter-Symbol Interference, i.e., “control-ISI.”

[0006] The above described problems which can occur during the first REQassertion are not relevant to subsequent REQs because the bus voltagelevel is no longer at the quiescent negated level and thus subsequentlytransmitted REQ do not require as large a voltage swing before beingsensed by REQ data detection circuitry.

[0007] Referring to FIG. 3, a similar problem occurs when the user datasignal is unchanged (all zeros or ones) for a prolonged period of time.A prolonged unchanged user data signal allows the user data voltagelevel to approach the negated quiescent voltage level. Subsequenttransitions in the user data signal from the negated quiescent voltagelevel require a large voltage swing in the data signal in order to besensed by the data detection circuitry. Again, there is a fixed periodof time for these data signal transitions to be sensed by data detectioncircuitry before another signal transition is asserted. However, thisperiod of time is often insufficient for the first data signaltransition to be sensed by the data detection circuitry, thereby causingthe data defined within this first large data signal transition to belost. This loss of user data occurring within the first user datatransition is hereby defined as digital data inter-symbol interference(“data-ISI”).

[0008] In transmitting data over a data bus, the trend is to increasethe frequency at which information can be transferred over the bus.However, an increase in data frequency causes a proportional decrease inthe time period allowable for control and data pulses to be sensed bythe data detection circuitry. Therefore, as data transmissionfrequencies are increased, there is a corresponding increase in bothcontrol-ISI as well as data-ISI as defined above. Minimizing bothcontrol and data-ISI is thus highly desirable.

SUMMARY OF THE INVENTION

[0009] An object of the present invention is to transmit data over adata bus with minimized digital control inter-symbol interference.

[0010] Another object of the present invention is to transmit data overa data bus with minimized digital data inter-symbol interference.

[0011] A first embodiment of the present invention comprises a methodfor transmitting data from a sending device (sender) to a receivingdevice (receiver) via a data bus in a manner to minimize control anddata inter-symbol interference. The method comprises the steps ofexecuting a start data transfer command, waiting for a FIFO register tocontain data, the FIFO register being coupled to a peripheral device,determining when the FIFO is holding data, driving the data held in theFIFO onto the data bus, inverting the data previously driven onto thebus to reduce the negated quiescent voltage level of the data bus,driving the inverted data, pausing for a predetermined period of time(t3), driving true data, pausing for a predetermined period of time(t1), asserting a REQ control signal, and pausing a predetermined periodof time, (t2), for data to be sensed by data detection circuitry. Thestep of pausing for the predetermined period of time, t2, provides REQdetection circuitry additional time to sense data being transmitted onthe data bus, thereby minimizing digital control inter-symbolinterference during data transmission from the sender to the receiver.

[0012] This method transmits data over the data bus with minimizeddigital control and data inter-symbol interference because the voltagelevel on the bus is not permitted to reach the bus negated quiescentvoltage level (the bus terminator voltage level) before a transitionoccurs. Even after a prolonged period of time where data signalstransmitted over the data bus have remained constant, an abrupttransition is not subjected to the lengthy transition necessitated bythe bus floating at the bus quiescent voltage level. Moreover,additional time is provided for the first REQ pulse to be detectedbefore subsequent REQ pulses are asserted. Accordingly, the first leveltransition occurring after the prolonged unchanged data transmissionlevel is detected by data detection circuitry within predefined datadetection circuitry time constraints.

[0013] These and other objects, advantages, aspects and features of thepresent invention will be more fully understood and appreciated uponconsideration of the following detailed description of a preferredembodiment, presented in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In the drawings:

[0015]FIG. 1 is a block diagram of a host computer system incorporatinga preferred embodiment of the present invention.

[0016]FIG. 2A is a circuit diagram of a single data signal path betweena sending device and a receiving device on the FIG. 1 bus.

[0017]FIG. 2B is signal flow diagram illustrating a REQ data signalerror conventionally transmitted over a data bus.

[0018]FIG. 3 is signal flow diagram illustrating a user data signalerror conventionally transmitted over a data bus.

[0019]FIG. 4 is a process flow diagram illustrating the method steps fortransmitting data from a sender to a receiver according to principles ofthe present invention.

[0020]FIG. 5 is signal flow diagram illustrating a REQ data signaltransmitted over a data bus according to principles of the presentinvention.

[0021]FIG. 6 is an expanded process flow diagram illustrating the methodsteps for transmitting data from a sender to a receiver according toanother embodiment of the present invention.

[0022]FIG. 7 is signal flow diagram illustrating a user data signaltransmitted over a data bus according to principles of the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0023] Referring again to FIG. 1, generally, the present inventioncomprises a method for bi-directionally transmitting data from a senderto a receiver via a data bus 15. In one instance, the sender is definedas a host computer system 10 and the receiver in defined as a peripheraldevice 5 for transmitting data from the host computer system 10 to theperipheral device 5. Alternatively, the sender is defined as theperipheral device 5 and the receiver is defined as the host computersystem 10 for transmitting data from the peripheral device to the hostcomputer system 10.

[0024] One preferred embodiment of the-present invention as set forthherein is a method for transmitting data from a disk drive 5 to hostcomputer system via data bus 15, such as a SCSI data bus, with minimizeddigital inter-symbol interference. Referring to FIG. 4, the methodcomprises the steps of executing a start data transfer command at step20 from the peripheral device 5 to the requesting host computer system10. The peripheral device 5 waits for a FIFO register (not shown) to beholding data at step 30. The FIFO register is physically associated orpositioned with the disk drive 5. Once data is detected as being held inthe FIFO at step 40, the data held in the FIFO is driven on to the busat step 50. At step 60 operation pauses for a first predetermined periodof time, t1, for the data to be set-up on the data bus, whereby asubsequent assertion of a REQ command at step 70 transfers data from thesender to the receiver. The first predetermined period of time typicallyranges from approximately 12.5 nano-seconds to 25 nano-seconds.

[0025] Since the REQ command has been asserted after a period of no datatransmissions, the next step is to pause for a second predeterminedperiod of time, t2 at step 80, so that the REQ pulse transition can besensed by detection circuitry and data associated therewith reliablysampled. The second predetermined period of time typically ranges fromapproximately 25 nanoseconds to 50 nano-seconds. As illustrated in FIG.5 this period of time, t2, is substantially longer in duration thantypical pauses that are interleaved between subsequent synchronous datatransmissions, e.g. t1. The period of time, t2, is substantially longerin order to provide the REQ data detection circuitry additional time tosense the first REQ data signal transition and to accurately sample theREQ data transferred over the data bus 15. In this manner, datatransmission over the data bus 15 is accomplished with minimized digitalcontrol inter-symbol interference. After the first REQ data signaltransition has been sensed, the voltage level of the REQ data signalwill be lower than the negated quiescent voltage level and thusadditional time is not necessary for subsequent REQ data to be sensed.

[0026] Referring to FIGS. 6 and 7, another preferred embodiment of thepresent invention adds additional steps to the FIG. 4 flow chart andfurther comprises loading a Data ISI counter at step 72 after assertinga REQ in step 70. The Data ISI counter counts the number of datasegments transmitted over the data bus. After a predetermined number ofData ISI counter count cycles and if there is still data to betransferred, the process steps restart at step 30.

[0027] The method steps of this embodiment further include the steps ofinverting and driving the data at step 52, that had been previouslydriven on to the data bus in step 50. Then the process is paused for athird predetermined period of time, t3 at step 54 to insure that thedata bus 15 voltage level does not reach the negated quiescent voltagelevel during subsequent steps of driving true data at step 56. The thirdpredetermined period of time typically ranges from approximately 12.5nano-seconds to 25 nano-seconds. Moreover, during subsequent steps ofdriving true data at step 56, the data bus voltage does not reach thenegated quiescent voltage level for a predetermined period of time asdefined by the data ISI counter in step 72. This reduction in thenegated quiescent voltage level of the data bus 15, achieved at steps5256, enables subsequent data segments transmitted over the data bus 15to be sensed faster by data detection circuitry 13. The subsequent datasegments are detected faster because the voltage level on the data bus15 is lower than the bus negated quiescent voltage level as shown inFIG. 7. Therefore, subsequent data segment transitions comprise smallervoltage swings before being detected by the data detection circuitry.These smaller voltage swings made by data transitions are more likely tobe detected within time constraints of the data detection circuitry thandata transitions that make larger voltage swings.

[0028] The subsequent data segments transmitted over the data bus followthe method steps of: deasserting the REQ drive command at step 100 andthen determining if the FIFO is holding data at step 110. If the FIFO isstill holding data, then driving the data held in the FIFO on to thedata bus at step 105, and then pausing for a predetermined period oftime, t1 at step 61, for data to be set up on the data bus, i.e., set uptime.

[0029] Thereafter, the REQ pulse is asserted at step 130 by theperipheral device 5 for transferring a data segment in response to adata request by the host computer system 10 for the next data segment.Accordingly, the data is transmitted from the disk drive 5 to the host10 over the bus 15. Then the step of pausing for a period of time, t1 atstep 62, is carried out so that data held on the data bus can be sensedby data detection circuitry, i.e., hold time. In one preferredimplementation, the set up time equals the hold time, however equalityis not required. Next, the REQ drive command is deasserted at step 140.Then, the Data ISI counter is decremented at step 150 and the Data ISIcounter is checked at step 160 to determine if the counter has reachedzero.

[0030] The FIFO is again checked at step 110 to determine whether theFIFO is holding data.

[0031] Further, if the FIFO is again determined to be holding data atstep 110, then the method steps 105, 61, 130, 62, 140, 150, and 160described above are repeated, if the Data ISI counter is not zero atstep 160 and the FIFO is still holding data at step 110, then thesesteps 105, 61, 130, 62, 140, 150, and 160 described above are cyclicallyrepeated until the FIFO is determined not be holding data at step 110 orthe Data ISI counter is equal to zero as determined at step 160.

[0032] Conversely, if it is determined that the FIFO is not holding dataat step 110, then it is determined if the last data segment has beentransferred at step 170. If the last data segment has been transferred,then the data transfer method ends at step 180. If, however, the lastdata segment has not been transferred, then the data transfer methodagain waits for the FIFO to be holding data at step 30 and repeats theFIG. 6 steps for transferring data over the data bus 15.

[0033] Additionally, if the Data ISI counter is equal to zero asdetermined at step 160, then it is again determined if the last datasegment has been transferred at step 170. If the last data segment hasbeen transferred, then the data transfer method ends at step 180. If,however, the last data segment has not been transferred, then the datatransfer method again waits for the FIFO to be holding data at step 30and repeats the FIG. 6 steps for transferring data over the data bus 15,until all of the data has been transferred.

[0034] It is important to note that the pause for a period of time, t2at step 80, is longer in duration than the pause for a period of time,t1 at step 60. The pause period, t2 at step 80, is asserted for theinitial data segment transferred over the data bus 15 as illustrated inFIG. 5. Additionally, the pause period, t2 at step 80, is also assertedwhen data transfers over the data bus 15 are paused for any reason or ifthe data ISI counter equals zero at step 160. In summary, the pauseperiod, t2 at step 80, is asserted during initial start data transfersat step 20; when the data transfers are paused for any reason; or whenthe data ISI counter equals zero at step 160. The pause period, t1 atstep 60, is asserted during synchronous data segment transfers.

[0035] The Data ISI counter (not shown) is a programmable register thatmay be programmed to count data segments over a range of approximately 1to 31 counter count cycles. Each count cycle represents a data segmenttransmitted over the data bus 15. Thus, once the ISI counter hasdecremented to zero, the above described method steps are againrestarted at the steps of determining if the last data segment has beentransferred at step 170 and if so then ending at step 180 and if notthen waiting for the FIFO to be holding data at step 30 and restartingthe data transfer process.

[0036] This restart of the data transfer process causes the data linesof the data bus 15 to be cleared of digital control/data inter-symbolinterference after a predetermined number of counter count cycles inaccordance with the preprogrammed Data ISI counter value. Likewise, arestart occurs if the FIFO is determined to be no longer holding data instep 110 and if it is determined in step 170 that the last data segmenthas not been sent. Therefore, if either the Data ISI counter has reachedzero in step 160 or if the last data segment has not been sent in step170, then the method for transferring data over the data bus 15 restartsat the step of waiting for the FIFO to be holding data at step 30.

[0037] Referring again to FIG. 1, another aspect of the inventionincludes the step of individually monitoring each data line of the databus with a 16-bit data activity detector 17. The data activity detector17 is connected to each of the data lines defined within the data bus15. When a monitored line is inactive for a period of time, the FIG. 6method steps are repeated for each individual data line of the data bus15.

[0038] Referring to FIGS. 1-7, a method for transmitting data from ahost computer system 10 to a peripheral device via a data bus 15,comprises the method steps of replacing the REQ command with an ACKcommand and repeating the method steps described above.

[0039] The above described method for transmitting data over a data bushas many advantages over the prior art, such as, starting data transferson a data bus, after the data bus has been at idle for a prolongedperiod of time, with minimized inter-symbol interference.

[0040] Another advantage of the above described method for transmittingdata over a multi-line data bus is directed to synchronouslytransmitting data over the data bus with minimized digital datainter-symbol interference even though any one of the data lines hasremained in an unchanged state for a prolonged period of time.

[0041] The data transfer rate, according to principle of the presentinvention, can be increased because the data bus need not compensate fordigital control inter-symbol interference realized after restarting thedata bus after prolonged periods of time at idle. Moreover, the datatransfer rate of the bus can be increased because the data bus need notcompensate for digital data inter-symbol interference realized afterprolonged synchronous data transfers of unchanged data values.

[0042] Having thus described an embodiment of the invention, it will nowbe appreciated that the objects of the invention have been fullyachieved, and it will be understood by those skilled in the art thatmany changes in construction and widely differing embodiments andapplications of the invention will suggest themselves without departingfrom the spirit and scope of the invention. The disclosure and thedescription herein are purely illustrative and are not intended to be inany sense limiting.

What is claimed is:
 1. A method for controlling transmission of datafrom a sender to a receiver via a data bus to minimize digitalinter-symbol interference, comprising the steps of: (A) executing astart data transfer command; (B) waiting for a FIFO register at thesender to be holding data and determining when the FIFO is holding data;(C) driving the data held in the FIFO on to the data bus; (D) pausing afirst predetermined period of time for the data to be set up on the databus; and (E) asserting a REQ command; (F) pausing a second predeterminedperiod of time longer than the first predetermined period of time fordata to be sensed by data detection circuitry, wherein pausing for thesecond predetermined period of time provides REQ detection circuitryadditional time to sense data being transmitted on the data bus, therebyminimizing digital inter-symbol interference during data transmissionfrom the sender to the receiver.
 2. The method of claim 1, wherein afterstep (C) the method further comprises the steps of: (G) inverting thedata driven on to the bus in step (C); (H) pausing a third predeterminedperiod of time so that a quiescent voltage level is not reached on thedata bus during subsequent steps of driving data; and (I) driving dataonto the data bus.
 3. The method of claim 2, wherein after step (E) themethod further comprising the steps of: (J) loading a Data ISI counterwith a predetermined count value; and after step (F), the method furtherincludes the steps of: (K) deasserting the REQ command; (L) determiningif the FIFO is holding data, (i) if the FIFO is holding data thencontinuing on to step (M), (ii) if the FIFO is not holding data thendetermining if the last data segment has been transferred, (iii) if itis determined that the last data segment has been transferred thenending, (iv) if it is determined that the last data segment has not beentransferred then repeating step (B), (M) driving a segment of data heldin the FIFO on to the data bus; (N) pausing the first predeterminedperiod of time for data to be sensed by data detection circuitry; (O)asserting a REQ command for transferring a data segment; (P) repeatingstep (N) (Q) deasserting the REQ command; (R) decrementing the data ISIcounter; and (S) determining if the Data ISI counter is zero, (v) if itis determined that the Data ISI counter is zero then determining if thelast data segment has been transferred, (vi) repeating steps (iii) and(iv).
 4. The method of claim 3, wherein steps (L)-(S) are cyclicallyrepeated until it is determined that the last data segment has beentransferred.
 5. The method of claim 3, wherein steps (L)-(S) arecyclically repeated until it is determined that the Data ISI counter isequal to zero.
 6. The method of claim 3, wherein the ISI counter may beprogrammed over a range of approximately 1 to 31 counts.
 7. The methodof claim 3, wherein the data bus is a SCSI data bus.
 8. The method ofclaim 3, wherein the data bus comprises a plurality of individual datalines and further comprising a data activity detector connected to thedata bus for monitoring data segment transfers on each individual dataline of the data bus.
 9. The method of claim 8, wherein steps (A)-(S)are repeated for each individual data line connected to the dataactivity detector.
 10. The method of claim 9, wherein the data activitydetector is a 16 bit data activity detector.
 11. The method of claim 3,wherein the sender is defined as a peripheral device and the receiver isdefined as a host computer system.
 12. The method of claim 3, whereinthe REQ command is replaced with an ACK command and the sender isdefined as a host computer system and the receiver is defined as aperipheral device.